This invention relates generally to test systems for integrated cicuits, and, more particularly, to a laser testing method for characterizing critical timing paths and analyzing timing related failure modes in high clock rate very large scale integrated microcircuits.
One of the most important requirements in the design and production of complex integrated microcircuits is to understand and control critical timing paths in the circuit. Timing analysis for portions of a microcircuit may be performed with circuit simulators, however, the complexity and shear size of a very large scale integrated microcircuit tends to place limitations on the use of such simulators. For example, such simulators may not include mechanisms for modeling "macro" effect on circuit performance such as substrate current distribution, power supply bussing, temperature patterns and patterns of gate delays which depend on starting materials or processing. Furthmore, there is a need for experimental measurement techniques for verifying such simulations done to identify critical internal timing paths in finished microcircuits.
In addition, a need exists in the area of acceptance testing of finished products. When performing electrical testing on large scale integrated circuits (microcircuits) or very large scale integrated circuits (microcircuits) the majority of the internal timing paths are not characterized with respect to internal timing conditions. Functional testing has done little more than validate the device truth table and perhaps test for certain data pattern sensitivities. While this has been sufficient for small scale technologies it does not provide an adequate performance screen for more complex devices. Even further, there exists a need for techniques useful for analyzing failed parts which exhibit frequency sensitivity failure modes. These may be much more difficult to analyze than catastrophic failures because the failure site may not have any distinguishing visual characteristics. Consequently, internal node electrical testing techniques are essential in locating the failure site. Non-destructive, automated techniques are therefore clearly needed in this area.
A basic problem in satisfying all of these needs is the difficulty of making reliable electrical measurements internally in a operating circuit. Low capacitance mechanical die probing is widely used but it is difficult to do quickly and non-destructively at many internal circuit nodes and would be difficult to automate.